1. Field of the Invention
The present invention relates to a buried word line structure and a method of fabricating the same, and more particularly to a buried word line structure which reduces the gate-induced drain leakage (GIDL) problem.
2. Description of the Prior Art
As device geometries shrink, reliability problems due to gate induced drain leakage forces the integrated circuit to operate at voltages which are lower than desired for best performance. When the device is biased, gate induced drain leakage results from the generation of electron-hole pairs in the surface of the depletion region of a transistor along the area where the gate conductor overlaps the drain diffusion region, such that the drain potential is more positive than the gate potential.
DRAM is a commonly-seen memory and is widely used in computers and other electronic appliances. DRAM includes a memory cell array composed of capacitors to store data. In a DRAM array, gate induced drain leakage degrades data retention time.
Therefore, there is a need to produce a structure which eliminates the gate induced drain leakage problem.